Roadmaps 🗺️

Beginner roadmap focused on physical design concepts in VLSI including Design for Testability (DFT) and SystemVerilog basics, building on knowledge of device structure and integration with a practical hardware description perspective. Beginner 80h vlsi physical-design dft systemverilog

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Topic Milestone Task Note Decision Project Grouped

AI Assist
Progress

Proof of Competence 0%

0 / 20 checkpoints declared

0/10 evidence needed for 100% — max 50% without proof

Foundations of Physical Design in VLSI

You can correlate device parameters to physical cell design and layout constraints Milestone

Analyze a basic MOSFET layout and identify key structural components (annotate transistor regions) Checkpoint

Draw a simple transistor-level layout using basic layout cells Project

You can apply design rules to create manufacturable layouts for a given technology node Milestone

Verify a layout for compliance against a given set of design rules (error-free report) Checkpoint

Introduction to Design for Testability (DFT) in VLSI

You can explain and implement basic scan chain insertion in a small design block Milestone

Insert scan chains into a simple combinational circuit and validate testability (can generate test vectors) Checkpoint

Create a scan-enabled flip-flop and simulate test mode operation Project

You can incorporate DFT structures through SystemVerilog and validate test coverage before tape-out Milestone

Write SystemVerilog code for a BIST controller and run functional simulation (observe test patterns triggered) Checkpoint

SystemVerilog Essentials for Physical Design

You can write and simulate basic SystemVerilog modules that represent hardware components Milestone

Develop a parameterized SystemVerilog module for a combinational block and verify output (testbench pass) Checkpoint

Create a SystemVerilog model of a multiplexer with timing checks Project

You can develop comprehensive testbenches to verify DFT features and assert design correctness Milestone

Implement SystemVerilog assertions for scan chain test modes and run coverage analysis (coverage goals met) Checkpoint

Practical Physical Design and DFT Workflows

You can follow a basic physical design flow and identify key challenge points such as congestion and timing violation Milestone

Perform a walkthrough of a basic physical design tool interface and produce a routed netlist (visual confirmation) Checkpoint

Execute a small-chip physical design cycle including synthesis and placement for a given RTL Project

You can manage DFT insertion and verify its physical impact on chip timing and layout quality Milestone

Simulate the impact of scan insertion on timing and power metrics (quantitative report) Checkpoint

Physical Design in VLSI (DFT, SystemVerilog) AI