Dive deep into the physical design phase of VLSI with an emphasis on Design for Testability (DFT) and the role of SystemVerilog, covering floorplanning, routing, clock tree synthesis, test insertion, and verification.
Intermediate
120h
vlsi
physical-design
dft
systemverilog
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Proof of Competence
0%
0 / 29 checkpoints declared
0/15 evidence needed for 100% — max 50% without proof
Introduction to Physical Design and Basics
You can describe the entire flow of physical design stages and how each contributes to chip functionality
Milestone
Outline a typical VLSI physical design flow including input and output files (flow diagram complete)
Checkpoint
You can explain primary DFT techniques and their trade-offs in test coverage and area overhead
Milestone
Create a test plan identifying appropriate DFT methods for a sample design (plan includes coverage goals)
Checkpoint
Floorplanning and Placement Essentials
You can create a viable floorplan that balances area, timing, and power goals
Milestone
Produce a floorplan layout for a moderate-sized design using EDA tools (layout meets design specs)
Checkpoint
Develop a floorplan for a hypothetical block with mixed macro and standard cells, managing power and signal routing
Project
You can apply placement algorithms to optimize standard cell placement for timing and congestion
Milestone
Run placement on a test design and analyze wirelength and congestion metrics (improvement vs. initial placement)
Checkpoint
Routing and Clock Tree Synthesis
You can perform both global and detailed routing to ensure signal integrity and minimal congestion
Milestone
Complete global routing for a block and validate congestion reports (all nets routed without violations)
Checkpoint
You can generate a clock tree that meets skew and latency constraints and integrates power optimization
Milestone
Implement CTS on a sample design and measure skew and insertion delay (meets skew target within bounds)
Checkpoint
Design a clock tree for a multi-clock domain chip with gating and buffer insertion, analyzing effects on power and timing
Project
Integration of DFT and Verification with SystemVerilog
You can develop SystemVerilog testbenches that validate DFT features and physical design constraints
Milestone
Write assertions to verify scan chain integrity and test signal timings (assertions cover key DFT points)
Checkpoint
Create a SystemVerilog-based testbench for a scan chain and simulate stuck-at faults injection
Project
You can apply verification flows that combine physical design data with simulation for robust DFT validation
Milestone
Run fault simulation and verify coverage goals for a DFT-enhanced design (coverage metrics exceed 90%)
Checkpoint
Advanced Topics and Optimization in Physical Design
You can optimize a physical design for power efficiency while respecting timing and area constraints
Milestone
Implement power gating on a sample design block and measure power savings via simulation (power reduced by ≥15%)
Checkpoint
You can identify EM/IR risks and perform signal integrity analyses, applying fixes to design layouts
Milestone
Complete an IR drop analysis on a floorplan and apply layout changes to reduce hotspots (IR drop under threshold)
Checkpoint
Analyze a design’s power grid for electromigration and implement a robust power distribution network
Project
Toolchains and Automation in Physical Design
You can automate key parts of the physical design flow and integrate DFT steps using scripting
Milestone
Script an automated flow for floorplanning to routing for a given netlist (fully automated run produces report)
Checkpoint
You can interpret physical design metrics and debug critical DRC/LVS errors for final design signoff
Milestone
Generate a full signoff report and resolve critical violations in a given layout (all major errors fixed)
Checkpoint
Build a dashboard for monitoring physical design flow metrics and visualize debug points interactively
Project